Caltech engineers collaborated with the University of Southampton in England to design an ultrahigh-speed data transfer chip. The chip integrates both an electronics chip and a photonics chip which uses light to transfer data. It took four years to complete, from the initial idea to the final test in the lab.
“As the world becomes increasingly connected, and every device generates more data, it is exciting to show that we can achieve such high data rates while burning a fraction of power compared to the traditional techniques. We had to optimise the entire system all at the same time, which enabled achieving a superior power efficiency,” said Azita Emami, the Andrew and Peggy Cherng Professor of Electrical Engineering and Medical Engineering, Executive Officer for Electrical Engineering and senior author of the paper.
The research paper is titled “A 100Gb/s PAM4 Optical Transmitter in A 3D-Integrated SiPh-CMOS Platform Using Segmented MOSCAP Modulators.” Rockley Photonics and the U.K. Engineering and Physical Sciences Research Council funded this research.
The need for high processing power and transmission creates the inevitable excess heat. Heat is the enemy of the speed and the amount of data a computer device can manage. It happens not just for personal computers or laptops but also for data centres.
While a laptop may heat up while when in use, servers in data centres also heat up as they work – but at a much grander scale. Therefore, managing heat in the data centre is essential. The less heat, the more computing power is generated and the greater the volume of information it can handle.
Hence, engineers tried to find a way to increase the processing speed while keeping the heat low. The solution was to design and co-optimise an electronics chip and a photonics chip. The chip is innovative because it integrates an electronic circuit essential for data processing, combined with a photonics chip which is the most efficient piece for data transmission.
The Caltech/Southampton integrated chip can transmit 100 gigabits of data per second! Moreover, the integrated chip generates minimal heat, producing just 2.4 pico-Joules per transmitted bit. The result increases the electro-optical power efficiency by 3.6 times compared to the current technology.
Handling Next-level Computing
In the future, data centres will manage very high volumes of data compared to today. The new design integrated chip will answer a continuous demand for increasing data communication speed in data centres and high-performance computers.
“As the computing power of the chips scale, the communication speed can become the bottleneck, especially under stringent energy constraints,” Emami explained.
The high-demand data transmission and processing from a data-demanding task, such as a video call, streaming a movie, or playing an online video game, need high processing power in the data centre.
“There are more than 2,700 data centres in the U.S. and more than 8,000 worldwide, with towers of servers stacked on top of each other to manage the load of thousands of terabytes of data going in and out every second,” says a Caltech graduate student Arian Hashemi Talkhooncheh (MS ’16), lead author of a paper describing the two-chip innovation that was published in the IEEE Journal of Solid-State Circuits.
